3-D Stacking and the Future of Integrated Circuits

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In the early 1970s, Intel co-founder Gordon E. Moore coined the famous Moore's Law, predicting that the number of transistors in integrated circuits (and by extension, processing power) would double each year from then on. Though more of an observational musing than a physical law, it has been remarkably accurate ever since.

The principle of Moore's Law correlates directly to how quickly technology has evolved over the last 50 years. The integrated circuits (ICs) that power our everyday electronics have become exponentially smaller, while their performance and memory capacity have grown exponentially larger. And, though it seems the law's relevance is on the decline, the practice of stacking integrated circuits into 3-D packages is making it relevant yet again, according to a study on temporary bonding materials and processes.

The practice of 3-D stacking involves stacking several ICs on top of one another instead of side by side. Thus, any given electronic device could pack two or more ICs into the same lateral space as a single circuit. However, the thickness of each individual circuit in that stack determines how much vertical space it takes up, which is often quite limited. If that remains the case, the trade-off isn't quite so appealing. The ideal solution, it seems, would be to make the IC substrate thinner and call it a day.

Well...sort of. In theory, a thinner substrate solves the space issue, sure. However, as with most manufacturing materials, the thinner these substrates get, the more fragile they become. While being turned into an integrated circuit, the silicon wafers undergo several harsh processes that can be highly detrimental to their integrity if they're too thin.

That's where we get to have some fun.

Temporary bonding allows us to briefly attach the main substrate to a carrier substrate (one that's a bit thicker) in order to fortify the very thin substrate during those harsh manufacturing processes. Then we remove the carrier, and we're left with an untarnished, but very thin, integrated circuit.

At Brewer Science, we're constantly in search of the best materials to make these processes smoother and simpler for you and your company. We've already implemented a simple and versatile debonding process that can be applied to almost any kind of substrate, which is highlighted in the above study.

And this is just the beginning. This new approach to integrated circuit packaging could very well define the future of microtechnology, and we're helping to push those boundaries every single day. As our processes improve, so do yours. Not only are we finding better ways to do things, but we're also building better products to help you do the same. Contact us today to see where we can take you.

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Brewer Science
Brewer Science

Brewer Science is a global technology leader in developing and manufacturing innovative materials, and processes for the fabrication of semiconductors and microelectronic devices. In 1981, Brewer Science revolutionized lithography processes with its invention of Brewer Science® ARC® anti-reflective coatings. Today, we continue to expand our technology portfolio to include products that enable advanced lithography, 3-D integration, chemical and mechanical device protection, nanotechnology, and thin wafer handling. With its headquarters in Rolla, Missouri, Brewer Science supports customers throughout the world with a service and distribution network in North America, Europe and Asia.

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