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Planarization: Leveling extreme topography for microelectronics

Fabrication of microelectronic devices increasingly involves the creation of high-aspect-ratio structures (those with large height or depth and narrow width, such as trenches, vias, columns, and mesas).  These structures provide isolation; serve as conduits for electrical, optical, or fluid signals; or enable pre-dicing before die singulation. New designs in semiconductor and MEMS devices are pushing the aspect ratios to the 10:1 range.  For semiconductors, these designs may take the form of trenches 600 nm deep and 60 nm wide. For MEMS, these may be vias 500 µm deep and 50 µm in diameter. After these structures are created, additional photolithographic processing of the wafers is necessary. The technology to create these high-aspect-ratio structures, however, has outpaced the ability of existing technologies to process photoresists over them.  This disparity has created a demand for materials that can level the surface of these processed wafers so that subsequent conventional photolithography processes can be used.

Topics: lithography, MEMS, planarization

Protecting front-side circuitry during backside DRIE processing

The demand for microelectromechanical systems (MEMS) requiring tall structure designs, as well as the increased density and performance expectations from the IC industry, are driving the need to utilize deep reactive ion etching (DRIE) in creating deep anisotropic etches of silicon for MEMS and semiconductor device applications. Vast yield hits are frequently the outcome of this process, where it is necessary to subject the front side of the substrate containing fragile, etch-sensitive circuitry to direct contact against the interior chuck of the etch chamber.

DRIE Advantages
Backside DRIE processes offer significant advantages over silicon wet-etch processes because of their ability to create very deep anisotropic vias. This ability allows manufacturers to maintain their target feature sizes during the entire etch. The DRIE process is frequently performed on substrates that have been previously subjected to costly processing steps necessary to create intricate device circuitry. These sensitive device features can be easily damaged as a result of undergoing the intense bombardment of plasma to the backside of the substrate. Additional benefits of DRIE processes include an increase in computational capacity utilizing flexible interconnects, increased electrical performance through shorter wire runs, and lower costs than existing CMOS techniques.

Topics: DRIE, MEMS, etching, CMOS, scratch-resistant