Tue, Jun 28, 2016 @ 10:30 AM
Light is energy.
Tue, Mar 08, 2016 @ 07:36 AM
In its constant quest to innovate, Brewer Science is continually on the cutting edge of what is next. We are currently combining directed self-assembly (DSA) and lithography to achieve sub–10 nm nanostructures. DSA uses block copolymers to generate arrays of self-assembled shapes such as lines or cylinders; the spatial arrangements of the resulting features can build complex structures for use in products such as cell phones and computer hard drives.
Tue, Mar 27, 2012 @ 04:00 AM
As semiconductor devices evolve, smaller and smaller feature sizes are required to achieve the performance desired by the consumer. Smaller features give rise to lower power consumption for mobile devices, less expensive devices due to the ability to manufacture more chips per wafer, and faster overall speed.
Tue, Feb 07, 2012 @ 04:00 AM
Cost of ownership plays an important role in lithography process materials and methods decisions. Process simplifications brought about by layer-to-layer synergy drive significant cost of ownership advantages for multilayer lithography systems such as the Brewer Science® OptiStack® system. Savings in mask engineering and manufacture are the greatest cost difference. Optical proximity correction (OPC) algorithms need only be determined once for all layers, rather than individually for each layer, which results in fewer mask corrections. Advanced devices with smaller critical dimensions benefit most from this system in that there are more layers at smaller critical dimensions, requiring greater mask design and production costs.
Tue, Jan 10, 2012 @ 10:41 AM
Fabrication of microelectronic devices increasingly involves the creation of high-aspect-ratio structures (those with large height or depth and narrow width, such as trenches, vias, columns, and mesas). These structures provide isolation; serve as conduits for electrical, optical, or fluid signals; or enable pre-dicing before die singulation. New designs in semiconductor and MEMS devices are pushing the aspect ratios to the 10:1 range. For semiconductors, these designs may take the form of trenches 600 nm deep and 60 nm wide. For MEMS, these may be vias 500 µm deep and 50 µm in diameter. After these structures are created, additional photolithographic processing of the wafers is necessary. The technology to create these high-aspect-ratio structures, however, has outpaced the ability of existing technologies to process photoresists over them. This disparity has created a demand for materials that can level the surface of these processed wafers so that subsequent conventional photolithography processes can be used.