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Planarization Innovations Help Semiconductors Go Even Smaller and More Complex

Imagine you’ve decided to undertake a home improvement project; you’re going to lay tile in the downstairs powder room.

Topics: planarization, semiconductors

Processing wafers with high-topography 3-D structures

43-µm deep pillars with oxide hard mask remainingExtreme trench fillingVia filling

Topics: TSV, planarization

Planarization: Leveling extreme topography for microelectronics

Fabrication of microelectronic devices increasingly involves the creation of high-aspect-ratio structures (those with large height or depth and narrow width, such as trenches, vias, columns, and mesas).  These structures provide isolation; serve as conduits for electrical, optical, or fluid signals; or enable pre-dicing before die singulation. New designs in semiconductor and MEMS devices are pushing the aspect ratios to the 10:1 range.  For semiconductors, these designs may take the form of trenches 600 nm deep and 60 nm wide. For MEMS, these may be vias 500 µm deep and 50 µm in diameter. After these structures are created, additional photolithographic processing of the wafers is necessary. The technology to create these high-aspect-ratio structures, however, has outpaced the ability of existing technologies to process photoresists over them.  This disparity has created a demand for materials that can level the surface of these processed wafers so that subsequent conventional photolithography processes can be used.

Topics: lithography, MEMS, planarization